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Maheedhar
Bhamidipati

VLSI Design Engineer FPGA & ML Enthusiast

Designing intelligent hardware systems
using FPGA and Artificial Intelligence.

View Projects My Resume Contact Me
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01.

About Me

I'm an M.Tech graduate in VLSI Design from Amrita Vishwa Vidyapeetham, Bengaluru, with strong hands-on experience in RTL design, SystemVerilog/UVM-based verification, and FPGA-based hardware prototyping.

My research bridges digital hardware and machine learning — implementing CNN, k-NN, and Decision Tree inference engines directly on FPGA silicon, achieving energy-efficient, real-time classification on ZYNQ-7 ZC702 platforms.

Proficient in pre-silicon validation, synthesis, STA fundamentals, and PPA analysis using industry EDA tools. Seeking entry-level Frontend VLSI roles across RTL design, verification, and pre-silicon validation.

4+ IEEE / Springer
Publications
3+ FPGA & VLSI
Projects
80% CNN Accuracy
on Hardware
MB
  • degree M.Tech VLSI Design
  • cgpa 7.53 / 10
  • institute Amrita Vishwa Vidyapeetham
  • location Bengaluru, India
  • focus RTL · Verification · FPGA
  • status ● Open to Work
02.

Technical Skills

▸ RTL Design & Verification

SystemVerilog Verilog UVM SVA (Assertions) Functional Verification Coverage-Driven Verification Testbench Development Pre-Silicon Validation

▸ EDA Tools

Xilinx Vivado ModelSim / QuestaSim Cadence Genus EDA Playgound Cadence Virtuoso

▸ Digital Design

RTL Micro-Architecture FSM Design Low-Power Design PPA Analysis Static Timing Analysis Timing Closure

▸ Hardware & Interfaces

FPGA Design ZYNQ-7000 AXI SPI I2C

▸ ML & Scripting

Python TCL Machine Learning CNN / Deep Learning Digital Image Processing MATLAB
03.

Work Experience

Jr. Embedded Systems Engineer

7s Technologies · July 2025 – Present

  • Developed a QR-based automated turnstile control system using Raspberry Pi 4B, enabling secure user access through QR code validation integrated with a centralized authentication server. The system ensures controlled entry by activating the turnstile mechanism for a defined duration upon successful verification.
  • Additionally, designed and implemented a multi-drone battery management system using STM32 (Blue Pill), featuring an automated X–Y positioning mechanism for precise battery handling, actuator-based insertion/removal, and RS-485 communication for reliable control. The system supports multi-slot charging for up to 12 batteries with efficient power management and coordination.
03.

Projects

⬡

AI-Driven EDA Tool for RTL Analysis & Verification

AI-powered RTL analysis and verification platform leveraging LLMs for automated Verilog/SystemVerilog parsing, syntax/functional error detection, code correction, and top-module extraction. Integrated ModelSim-based simulation, waveform generation, and circuit visualization into an end-to-end RTL debug workflow to accelerate verification and streamline hardware design analysis.

Python Verilog SystemVerilog ModelSim TCL LLMs
⬡

Lightweight Binary Image Classification on FPGA

RTL architectures accelerating ML inference (CNN, k-NN, Decision Tree) on FPGA. Parallel & pipelined datapaths achieving ~80% classification accuracy with real-time throughput on ZYNQ-7 ZC702. Pre-silicon verification using SystemVerilog testbenches and post-synthesis PPA analysis via Vivado.

Verilog SystemVerilog Xilinx Vivado ModelSim Python ZYNQ-7000
⬡

Fruit Ripeness Detection using CNN

CNN-based fruit ripeness classification using EfficientNetB0 and ResNet50 for tomatoes, papayas, and bananas. Achieved up to 78.67% accuracy with EfficientNetB0, improving tomato classification by 13.35% over prior methods via advanced transfer learning strategies.

Python EfficientNetB0 ResNet50 Transfer Learning Google Colab
⬡

Low-Power Adder Architecture Design

Power-efficient multiplexer-based ripple carry adder in synthesizable Verilog. Synthesis and PPA analysis via Cadence Genus achieved reduced power and area with minimal timing impact. Benchmarked multiple low-power adder architectures for optimal energy-efficient trade-offs.

Verilog Cadence Genus CMOS Design PPA Analysis Low-Power Design
⬡

Plant Leaf Disease Detection

Deep learning–based image classification pipeline for plant leaf disease identification using CNN and Inception-ResNet-V2 with transfer learning. Built a scalable, real-time inference pipeline supporting seamless integration with agricultural monitoring and management systems.

Python OpenCV CNN Inception-ResNet-V2 Transfer Learning
04.

Publications

IEEE Nov 2025

Accelerating Lightweight Binary Image Classification on FPGA Using Machine Learning Models

IEEE Xplore · Conference Paper

ieeexplore.ieee.org
IEEE July 2025

Ripeness Revolution: Harnessing CNN Models for Precise Fruit Classification

IEEE Xplore · Conference Paper

ieeexplore.ieee.org
Springer 2023

Determining the Fruit Ripening Stage Using Convolution Neural Networks

Springer Link · Book Chapter

link.springer.com
IJRPR 2023

Plant Leaf Disease Detection

International Journal of Research Publications & Reviews

ijrpr.com
05.

Resume

📄 Maheedhar_Bhamidipati_VLSI_Engineer.pdf
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06.

Contact

I'm actively looking for entry-level Frontend VLSI opportunities.
Feel free to reach out — let's build intelligent hardware together.

email

maheedharbh@gmail.com

phone

+91-7416964632

linkedin

maheedhar-bhamidipati

github

MaheedharBhamidipati